1. Field of the Invention
This invention relates to a static random access memory (SRAM) and, more particularly, to an internal synchronization type MOS SRAM having an address transition detecting circuit (ATD).
2. DESCRIPTION OF THE RELATED ART
This type of SRAM is disclosed in, for example, 1985 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS pp. 64, 65 and 306 "A 17ns 64K CMOS RAM with a Schmitt Trigger Sense Amplifier" Kiyofumi Ochii et. al.
In the specification pertaining to the above SRAM, the time interval between the recovery of write enable signal WE from "0" level to "1" level (from the write state to the readout state) and application of a readout address for the next cycle or the address transition is defined as write recovery time t.sub.WR. If the address is changed before write recovery time t.sub.WR has passed, data may be erroneously written in the next address. In general, write recovery time t.sub.WR is set to be greater than 0, and the address transition is inhibited in the write operation. However, the pulse width of address transition detection signal .phi..sub.ATD output from the ATD is set so as to attain the optimum readout operation, and the pulse is designed to terminate in synchronism with the rise of the word line potential. When the MOSFET is miniaturized, the time interval from the address transition to the rise of the word line potential is reduced according to the scaling rule. As a result of this, the pulse width of an equalizing pulse is reduced, and the operation margin for write recovery time t.sub.WR &lt;0 becomes extremely small, making it difficult to satisfy the specification of t.sub.WR =0.